1. Field of the Invention
The invention relates to the fabrication of semiconductor integrated circuit structures, and more particularly to the formation of buried word line structures in memory cells.
2. Description of the Related Art
Semiconductor memories store bits of information in arrays of memory cells. For example, a dynamic random access memory (DRAM) cell typically includes an access field effect transistor (FET) and a storage capacitor. Memory cell word and bit lines may be buried by forming trenches in a semiconductor substrate and filling the trench with metal. Storage capacitors can be formed on the substrate surface or in the metal layers disposed above the substrate. For example, some types of DRAM cells have buried split word lines formed above buried bit lines. Some types of memory cells have buried word and bit lines.
FIG. 1A is a perspective view of a conventional memory cell including buried word and bit lines. FIG. 1B is a cross-section view taken along the cut line A-A of FIG. 1A before buried word line trenches are formed. Referring to FIG. 1B, a silicon substrate 101 is initially covered with a nitride layer 108, such as silicon nitride (Si3N4) and the substrate 101 is etched off to a preset depth, which forms the bit line trenches 150. An oxide (silicon dioxide, SiO2) liner 102 is formed on the bottom and a portion of sidewalls of the bit line trenches 150 and a glue layer 103 is then formed over the oxide liner 102. Next, a metal is deposited over the glue layer 103 to form the bit lines 104 and nitride liner 108a is formed over the top of the metal 104 and a portion of sidewalls of the buried bit line trenches 150. Finally, the resulting spaces are filled with oxide 106.
Referring to FIG. 1A, a memory cell 100 includes buried bit and word lines 104, 116 coupled to a vertical access transistor 130 disposed in a semiconductor substrate 101. Vertically access transistors 130 are formed in semiconductor pillars that extend outwardly from an underlying substrate 101. Each of the vertically access transistors 130 include a first source/drain region 131, a channel region 132 and a second source/drain region 133. Nitride 108 is formed on the first source/drain region 131. The buried word lines 116 are arranged above the buried bit line 104 and extend in a trench 110 orthogonal to a buried bit line 104.
Since the word line trenches 110 are orthogonal to the bit line trenches 150, the silicon substrate 101 and the oxide layer 106 are alternatingly disposed along the word line trenches 110. Some problems arise during the subsequent etching of the word line trenches 110. First, since silicon and oxide have two different etching rates, etching depths of the silicon substrate 101 and the oxide layer 106 are entirely different, resulting in a rough sidewall and bottom surface along the word line trench 110. FIG. 1C is a cross-section view taken along the cut line A-A of FIG. 1A after buried word lines are formed. Here, gate oxide and a glue layer are designated by 114 and 115, respectively. As can be observed from the bottom of the word line trench 110 in FIGS. 1A and 1C, it is obvious that the etching depth of the silicon substrate 101 is deeper than that of the oxide layer 106, leading to a depth difference y at the bottom of the trench 110. Then, after a metal (not shown) such as Tungsten is filled and then recessed in the word line trench 110, two adjacent word lines 116 in the word line trench 110 are formed by etching away a center region of Tungsten (hereinafter referred to as “WL separating process”). During this WL separating process, in order to clean Tungsten from the bottom of the word line trench 110, the bottom of the word line trench 110 is subject to being over-etched, thereby resulting in a thinner or weaker isolation between the word lines 116 and the bit line 104. On the other hand, it is difficult to clean Tungsten from the bottom of the word line trench 110 and thus residues of Tungsten may cause a short circuit.
Further, the word line trenches 110 also have rough sidewalls for the same reason of different etching rates. More specifically, the oxide sidewalls are more protruding than the silicon sidewalls when the word line trenches 110 are initially formed. Accordingly, after the WL separating process is performed, the thickness of Tungsten along the oxide sidewalls is generally thinner than that along the silicon sidewalls. In general, the thinner the word line (or Tungsten), the more the resistance. The rough sidewalls seriously increase gate resistance. Even though there is a single word line disposed in the trench 116, its rough sidewalls and bottom also lack uniformity in gate resistance.